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K4N51163QC-ZC
512M gDDR2 SDRAM
512Mbit gDDR2 SDRAM
Revision 1.5 October 2005
Notice
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice. -1-
Rev 1.5 Oct. 2005
K4N51163QC-ZC
Revision History
Revision 1.0 1.1 Month April April Year 2005 2005 - First Released. - Corrected typo. History
512M gDDR2 SDRAM
1.2
May
2005
- Changed speed bin organization. (K4N56163QF-GC2A/K4N56163QF-GC33/K4N56163QF-GC36) - 533 Speed bin changed into 550 speed bin. - 600 speed bin is added. - 667 speed bin changed into 700 speed bin. - Corrected typo. - Seperaed gDDR2 device operation & timing. - Corrected typo. - Added gDDR2-800 SPEC - Revised the IDD current values. - Corrected typo. - Merged Device operation and timing diagram according to customer request
1.3 1.4 1.5
Jun September October
2005 2005 2005
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Rev 1.5 Oct. 2005
K4N51163QC-ZC
8M x 16Bit x 4 Banks graphic DDR2 Synchronous DRAM with Differential Data Strobe 1.0 FEATURES
* 1.8V + 0.1V power supply for device operation * 1.8V + 0.1V power supply for I/O interface * 4 Banks operation * Posted CAS * Programmable CAS Letency : 3,4,5 * Programmable Additive Latency : 0, 1, 2, 3 and 4 * Write Latency (WL) = Read Latency (RL) -1 * Burst Legth : 4 and 8 (Interleave/nibble sequential) * Programmable Sequential/ Interleave Burst Mode
512M gDDR2 SDRAM
* Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature) * Off-chip Driver (OCD) Impedance Adjustment * On Die Termination * Refresh and Self Refresh Average Refesh Period 7.8us at lower then TCASE 85xC, 3.9us at 85xC < TCASE < 95 xC * Lead Free 84 ball FBGA(RoHS compliant)
2.0 ORDERING INFORMATION
Part NO. K4N51163QC-ZC25 K4N51163QC-ZC2A K4N51163QC-ZC33 K4N51163QC-ZC36 Max Freq. 400MHz 350MHz 300MHz 275MHz Max Data Rate 800Mbps/pin 700Mbps/pin 600Mbps/pin 550Mbps/pin SSTL 84 Ball FBGA Interface Package
* K4N51163QC-ZC2A/36 can fully cover previsous K4N51163QF-ZC30/37(667Mbps/533Mbps) product. * K4N51163QC-GC is the Leaded package part number.
3.0 GENERAL DESCRIPTION
FOR 8M x 16Bit x 4 Bank gDDR2 SDRAM
The 512Mb gDDR2 SDRAM chip is organized as 8Mbit x 16 I/O x 4banks banks device. This synchronous device achieve high speed graphic double-data-rate transfer rates of up to 800Mb/sec/pin for general applications. The chip is designed to comply with the following key gDDR2 SDRAM features such as posted CAS with additive latency, write latency = read latency - 1, Off-Chip Driver(OCD) impedance adjustment and On Die Termination. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. A thirteen bit address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. For example, 512Mb(x16) device receive 13/10/2 addressing. The 512Mb gDDR2 devices operate with a single 1.8V 0.1V power supply and 1.8V 0.1V VDDQ. The 512Mb gDDR2 devices are available in 84ball FBGAs(x16).
Note : The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
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Rev 1.5 Oct. 2005
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4.0 PIN CONFIGURATION
Normal Package (Top View)
1 VDD UDQ6 VDDQ UDQ4 VDD LDQ6 VDDQ LDQ4 VDDL 2 NC VSSQ UDQ1 VSSQ NC VSSQ LDQ1 VSSQ VREF CKE NC BA0 A10 VSS A3 A7 VDD A12 3 VSS UDM VDDQ UDQ3 VSS LDM VDDQ LDQ3 VSS WE BA1 A1 A5 A9 NC A B C D E F G H J K L M N P R 7 8 VSSQ UDQS VDDQ UDQ2 VSSQ LDQS VDDQ LDQ2 VSSDL RAS CAS A2 A6 A11 NC 9 UDQS VSSQ UDQ0 VSSQ LDQS VSSQ LDQ0 VSSQ CK CK CS A0 A4 A8 NC
512M gDDR2 SDRAM
VDDQ UDQ7 VDDQ UDQ5 VDDQ LDQ7 VDDQ LDQ5 VDD ODT
VDD
VSS
Note : VDDL and VSSDL are power and ground for the DLL. lt is recommended that they are isolated on the device from VDD, VDDQ, VSS, and VSSQ.
1 2 3 4 5 6 7 8 9
Ball Locations
: Populated Ball + : Depopulated Ball
A B C D E F
Top View (See the balls through the Package)
G H J K L M N P R
+ + +
+ + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + +
+ + +
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5.0 PACKAGE DIMENSIONS (84 Ball FBGA)
11.00 0.10 6.40 0.80 1.60
512M gDDR2 SDRAM
# A1 INDEX MARK (OPTIONAL)
9
A B C D E F
8
7
6
5
4
3
2
1
K K
5.60
L M N R
3.20 84-0.450.05
0.2 M A B (0.90) (1.80)
(6.15)
1.60
0.80
J
13.00 0.10 0.10MAX
H
11.00 0.10 #A1
13.00 0.10
11.20
G
0.350.05 MAX.1.20
0.500.05
Unit : mm
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Rev 1.5 Oct. 2005
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6.0 INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol CK, CK Type Input Function
512M gDDR2 SDRAM
Clock: CK and CK are differential clock inputs. CMD, ADD inputs are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during powerdown. Input buffers, excluding CKE, are disabled during self refresh. Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. On Die Termination: ODT (registered HIGH) enables termination resistance internal to the gDDR2 SDRAM. When enabled, ODT is only applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal for x16 configurations. The ODT pin will be ignored if the Extended Mode Register (EMRS) is programmed to disable ODT. Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Bank Address Inputs: BA0 and BA1 define to which bank an Actove, Read, Write or Precharge command is being applied. BA0 also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. Address Inputs: Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during Mode Register Set commands.
CKE
Input
CS
Input
ODT RAS, CAS, WE (L)UDM
Input Input Input
BA0 - BA1
Input
A0 - A12
Input
DQ
Input/ Data Input/ Output: Bi-directional data bus. Output Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15. The data Input/ strobes LDQS and UDQS may be used in single ended mode or paired with optional complementary sigOutput nals LDQS and UDQS to provide differential pair signaling to the system during both reads and writes. An EMRS(1) control bit enables or disables all complementary data strobe signals. No Connect: No internal electrical connection is present. Supply DQ Power Supply: 1.8V 0.1V Supply DQ Ground Supply DLL Power Supply: 1.8V 0.1V Supply DLL Ground Supply Power Supply: 1.8V 0.1V Supply Ground Supply Reference voltage
LDQS,(LDQS) UDQS,(UDQS) NC/RFU VDDQ VSSQ VDDL VSSL VDD VSS VREF
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7.0 ABSOLUTE MAXIMUM DC RATINGS
Symbol VDD VDDQ VDDL VIN, VOUT TSTG Parameter Voltage on VDD pin relative to Vss Voltage on VDDQ pin relative to Vss Voltage on VDDL pin relative to Vss Voltage on any pin relative to Vss Storage Temperature Rating
512M gDDR2 SDRAM
Units V V V V C Notes 1 1 1 1 1, 2
- 1.0 V ~ 2.3 V - 0.5 V ~ 2.3 V - 0.5 V ~ 2.3 V - 0.5 V ~ 2.3 V -55 to +100
Note : 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD512 standard.
8.0 AC & DC OPERATING CONDITIONS
8.1 Recommended DC Operating Conditions (SSTL - 1.8)
Symbol VDD VDDL VDDQ VREF VTT Parameter Supply Voltage Supply Voltage for DLL Supply Voltage for Output Input Reference Voltage Termination Voltage Rating Min. 1.7 1.7 1.7 0.49*VDDQ VREF-0.04 Typ. 1.8 1.8 1.8 0.50*VDDQ VREF Max. 1.9 1.9 1.9 0.51*VDDQ VREF+0.04 Units V V V mV V 4 4 1,2 3 Notes
Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal to VDD. 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC). 3. VTT of transmitting device must track VREF of receiving device. 4. AC parameters are measured with VDD, VDDQ and VDDDL tied together.
8.2 Operating Temperature Condition
Symbol TOPER Parameter Operating Temperature Rating 0 to 95 Units C Note 1, 2, 3
Note : 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard. 2. At 0 - 85 C, operation temperature range are the temperature which all DRAM specification will be supported. 3. At 85 - 95 C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
8.3 Input DC & AC Logic Level
Input DC Logic Level Symbol VIH(DC) VIL(DC) Input AC Logic Level Symbol VIH(AC) VIL(AC) Parameter DC input logic high DC input logic low Min. VREF + 0.125 VDDQ - 0.3 Max. VDDQ + 0.3 VREF - 0.125 Units V V Note
Parameter AC input logic high AC input logic low
Min. VREF + 0.250 -
Max. VREF - 0.250
Units V V
Note
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8.4 AC Input Test Conditions
Symbol VREF VSWING(MAX) SLEW Condition Input reference voltage Input signal maximum peak to peak swing Input signal minimum slew rate Value 0.5 * VDDQ 1.0 1.0
512M gDDR2 SDRAM
Units V V V/ns Note 1 1 2, 3
Note : 1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative transitions.
VDDQ VIH(AC) min VSWING(MAX) VIH(DC) min VREF VIL(DC) max VIL(AC) max delta TF Falling Slew = VREF - VIL(AC) max delta TF delta TR Rising Slew = VSS VIH(AC) min - VREF delta TR
< AC Input Test Signal Waveform >
8.5 Differential input AC logic Level
Symbol VID(AC) VIX(AC) Parameter AC differential input voltage AC differential cross point voltage Min. 0.5 0.5 * VDDQ - 0.175 Max. VDDQ + 0.6 0.5 * VDDQ + 0.175 Units V V Note 1 2
Note : 1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to VIH(AC) - VIL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC) indicates the voltage at which differential input signals must cross.
VDDQ VTR VID VCP VSSQ Crossing point VIX or VOX
< Differential signal levels >
8.6 Differential AC output parameters
Symbol VOX(AC) Parameter AC differential cross point voltage Min. 0.5 * VDDQ - 0.125 Max. 0.5 * VDDQ + 0.125 Units V Note 1
Note : 1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at which differential output signals must cross.
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8.7 OCD default characteristics
Description Output impedance Output impedance step size for OCD calibration Pull-up and pull-down mismatch Output slew rate Sout Parameter Min Nom
512M gDDR2 SDRAM
Max Unit ohms ohms ohms V/ns Note 1,2 6 1,2,3 1,4,5,6,7,8
Normal 18ohms See full strength default driver characteristics 0 0 1.5 1.5 4 5
Notes: 1. Absolute Specifications (0C TCASE +95C; VDD = +1.8V 0.1V, VDDQ = +1.8V 0.1V) 2. Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV. 3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage. 4. Slew rate measured from VIL(AC) to VIH(AC). 5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaranteed by design and characterization. 6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process and represents only the DRAM uncertainty. Output slew rate load : VTT
25 ohms Output (VOUT) Reference Point
7. DRAM output slew rate specification applies to 533Mb/sec/pin, 667Mb/sec/pin, 800Mb/sec/pin, 900Mbps/sec/pin and 1000Mbps/sec/pin speed bins. 8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS specification.
8.8 DC characteristics
Parameter
Operating Current (One Bank Active)
(Recommended operating conditions unless otherwise noted, 0C Tc 85C )
Symbol
Test Condition
Burst Length=4 tRC tRC(min). IOL=0mA, tCC= tCC(min). DQ,DM,DQS inputs changing twice per clock cycle. Address and control inputs changing once per clock cycle CKE VIL(max), tCC= tCC(min) CKE VIH(min), CS VIH(min),tCC= tCC(min) Address and control inputs changing once per clock cycle CKE VIL(max), tCC= tCC(min) Fast PDN Exit MRS(12) = 0mA Slow PDN Exit MRS(12) = 1mA
Version -25
TBD
-2A
140
-33
TBD
-36
130
Unit
ICC1
mA
Precharge Standby Current ICC2P in Power-down mode Precharge Standby Current ICC2N in Non Power-down mode Active Standby Current power-down mode
TBD TBD TBD TBD 40 30 12
10 TBD TBD TBD 35 25
mA mA
ICC3P
mA 12
Active Standby Current in in Non Power-down mode
ICC3N
CKE VIH(min), CS VIH(min), tCC= tCC(min) DQ,DM,DQS inputs changing twice per clock cycle. Address and control inputs changing once per clock cycle IOL=0mA ,tCC= tCC(min), Page Burst, All Banks activated. DQ,DM,DQS inputs changing twice per clock cycle. Address and control inputs changing once per clock. tRC tRFC CKE 0.2V Burst Length=4 tRC tRC(min). IOL=0mA, tCC= tCC(min). DQ,DM,DQS inputs changing twice per clock cycle. Address and control inputs changing once per clock cycle
TBD
60
TBD
55
mA
Operating Current ( Burst Mode) Refresh Current Self Refresh Current Operating Current (4Bank interleaving)
ICC4
TBD
200
TBD
170
mA
ICC5 ICC6 ICC7
TBD TBD TBD
160 8 350
TBD TBD TBD
165 8 320
mA mA mA
Note : 1. Measured with outputs open and ODT off
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8.9 Input/Output capacitance
Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, DQS Symbol CCK CDCK CI CDI CIO CDIO - 36 Min 1.0 x 1.0 x 2.5 x Max 2.0 0.25 2.0 0.25 4.0 0.5 Min 1.0 x 1.0 x 2.5 x -33 Max 2.0 0.25 2.0 0.25 4.0 0.5
512M gDDR2 SDRAM
- 2A Min 1.0 x 1.0 x 2.5 x Max 2.0 0.25 2.0 0.25 3.5 0.5 1.0 x 1.0 x 2.5 x - 25 Min Max 2.0 0.25 1.75 0.25 3.5 0.5
Units pF pF pF pF pF pF
9.0 Electrical Characteristics & AC Timing for - 25/2A/33/36
(0 C < TCASE < 95 C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)
9.1 Refresh Parameters
Parameter Refresh to active/Refresh command time Average periodic refresh interval tREFI Symbol tRFC 0 C TCASE 85C 85 C < TCASE 95C 512Mb 105 7.8 3.9 Units ns s s
9.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS
SPEED Bin (CL-tRCD-tRP) Parameter CAS LATENCY tCK tRCD tRP tRC tRAS -25 5-5-5 min 5 2.5 5 5 21 16 - 2A 5-5-5 min 5 2.86 5 5 18 13 -33 5-5-5 min 5 3.3 5 5 18 13 - 36 4-4-4 min 4 3.6 4 4 15 11 tCK ns tCK tCK tCK tCK Units
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9.3 Timing Parameters by Speed Grade
Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period Clock cycle time, CL= x DQ and DM input hold time DQ and DM input setup time Control & Address input pulse width for each input DQ and DM input pulse width for each input Data-out high-impedance time from CK/ CK DQS low-impedance time from CK/CK DQ low-impedance time from CK/CK Symbol tAC tDQSCK tCH tCL tHP tCK tDH tDS tIPW tDIPW tHZ tLZ (DQS) - 25 min -400 -350 0.45 0.45 min(tCL, tCH) 2500 125 50 0.6 0.35 x tAC min max +400 +350 0.55 0.55 x 8000 x x x x tAC max tAC max tAC max 200 300 x 0.25 x x x x x 0.6 x x x 1.1 0.6 x x min -450 -400 0.45 0.45 min (tCL, tCH) 2.86 175 50 0.6 0.35 x tAC min 2*tAC min x x tHP tQHS WL -0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 325 200 0.9 0.4 7.5 10 - 2A max +450 +400 0.55 0.55 x 8.0 x x x x tAC max tAC max tAC max 310 410 x WL +0.25 x x x x x 0.6 x x x 1.1 0.6 x x min -470 -420 0.45 0.45 min (tCL, tCH) 3.3 195 70 0.6 0.35 x tAC min 2*tAC min x x tHP tQHS WL -0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 345 220 0.9 0.4 7.5 10
512M gDDR2 SDRAM
(Refer to notes for informations related to this table at the bottom)
- 33 max +470 +420 0.55 0.55 x 8.0 x x x x tAC max tAC max tAC max 320 420 x WL +0.25 x x x x x 0.6 x x x 1.1 0.6 x x min
- 36 max +500 +450 0.55 0.55 x 8.0 x x x x tAC max tAC max tAC max 340 440 x WL +0.25 x x x x x 0.6 x x x 1.1 0.6 x x -500 -450 0.45 0.45 min (tCL, tCH) 3.6 225 100 0.6 0.35 x tAC min 2* tAC min x x tHP tQHS WL -0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 375 250 0.9 0.4 7.5 10
Units Notes ps ps tCK tCK ps ns ps ps tCK tCK ps ps ps ps ps ps tCK tCK tCK tCK tCK tCK tCK tCK ps ps tCK tCK ns ns 14,16, 18 14,16, 18 28 28 12 12 19 27 27 22 21 20,21 24 15,16, 17 15,16, 17
tLZ(DQ) 2*tAC min x x tHP tQHS -0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 250 175 0.9 0.4 7.5 10
DQS-DQ skew for DQS and associated tDQSQ DQ signals DQ hold skew factor DQ/DQS output hold time from DQS Write command to first DQS latching transition DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time Write postamble Write preamble Address and control input hold time Address and control input setup time Read preamble Read postamble Active to active command period for 1KB page size products Active to active command period for 2KB page size products tQHS tQH tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPST tWPRE tIH tIS tRPRE tRPST tRRD tRRD
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Parameter CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay Exit self refresh to a non-read command Exit self refresh to a read command Exit precharge power down to any non-read command Exit active power down to read command Exit active power down to read command (Slow exit, Lower power) CKE minimum pulse width (high and low pulse width) ODT turn-on delay ODT turn-on Symbol tCCD tWR - 25 min 2 6 x x max min 2 5 tWR +tRP 3 3 tRFC + 10 200 x x 2 2 6 - AL 3 2 2 2 tAC (max)+0 .7 x x x x x - 2A max min 2 5 tWR +tRP 3 3 tRFC + 10 200 2 2 6 - AL 3 2 tAC (min)
512M gDDR2 SDRAM
-33 max x x x min 2 4 tWR +tRP 2 2 tRFC + 10 200 x x 2 2 6 - AL 3 2 tAC (max)+0 .7 2 tAC (min) 2 tAC (max)+1 x x x x x - 36 max Units Notes tCK tCK tCK tCK tCK ns tCK tCK tCK 9 11 23
tDAL WR+tRP tWTR tRTP 3 3
tXSNR tRFC + 10 tXSRD tXP tXARD 200 2 2
tXARDS 8 - AL tCKE tAOND 3 2
tCK 9, 10 tCK tCK ns 13, 25
tAON tAC(min)
tAC(max tAC )+0.7 (min)
ODT turn-on(Power-Down mode) ODT turn-off delay ODT turn-off
tAONPD tAOFD
2tCK+tA 2tCK+ 2tCK+ 2tCK+tA tAC(min) tAC tAC tAC C(max)+ tAC(max tAC(max C(max)+ +2 (min)+2 (min)+2 (min)+2 1 )+1 )+1 1 2.5 2.5 2.5 2.5 tAC (max)+ 0.6 2.5 tAC (min) 2.5 tAC (max)+ 0.6 2.5 tAC (min) 2.5 tAC (max)+ 0.6
ns tCK ns 26
tAOF tAC(min)
tAC(max tAC )+ 0.6 (min)
ODT turn-off (Power-Down mode) ODT to power down entry latency ODT power down exit latency OCD drive mode output delay
tAOFPD tANPD tAXPD tOIT
2.5tCK+ 2.5tCK+t 2.5tCK+t 2.5tCK+ tAC(min) tAC(min) tAC(min) tAC(min) tAC(max AC(max) AC(max) tAC(max ns +2 +2 +2 +2 )+1 +1 +1 )+1 3 8 0 12 3 8 0 tIS+tCK +tIH 12 3 8 0 tIS+tCK +tIH 12 3 8 0 tIS+tCK +tIH 12 tCK tCK ns ns 24
Minimum time clocks remains ON after tIS+tCK tDelay CKE asynchronously drops LOW +tIH
Note : General notes, which may apply for all AC parameters
1. Slew Rate Measurement Levels a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between DQS - DQS = -500 mV and DQS - DQS = +500mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device. b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VREF - 125 mV to VREF + 250 mV for rising edges and from VREF + 125 mV and VREF - 250 mV for falling edges. For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to CK - CK = +500 mV (250mV to -500 mV for falling egdes). c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential strobe.
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K4N51163QC-ZC
512M gDDR2 SDRAM
2. gDDR2 SDRAM AC timing reference load Following figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). VDDQ
DQ DQS DQS
DUT
Output Timing reference point 25
VTT = VDDQ/2

The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal. 3. gDDR2 SDRAM output slew rate test load Output slew rate is characterized under the test conditions as shown in the following figure. VDDQ DUT
DQ DQS, DQS
Output Test point 25
VTT = VDDQ/2

4. Differential data strobe gDDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the gDDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 ohm to 10 K ohm resisor to insure proper operation. DQS/ DQS
DQS DQS tWPRE
VIH(ac) VIH(dc)
tDQSH
tDQSL
tWPST
DQ
D
VIL(ac)
D
D
VIL(dc)
D tDH
VIH(dc)
tDS
VIH(ac)
tDS DMin
tDH DMin
DM
DMin
DMin
VIL(dc)

tCH CK tCL
VIL(ac)
CK/CK
CK
DQS
DQS/DQS
DQS tRPRE tRPST Q tDQSQmax tQH Q Q tDQSQmax tQH Q
DQ

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512M gDDR2 SDRAM
5. AC timings are for linear signal transitions. 6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 7. All voltages are referenced to VSS. 8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. : Specific Notes for dedicated AC parameters 9. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing. 10. AL = Additive Latency 11. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and tRAS(min) have been satisfied. 12. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency 13. Timings are guaranteed with command/address input slew rate of 1.0 V/ns. 14. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 15. Timings are guaranteed with data, mask, and (DQS in singled ended mode) input slew rate of 1.0 V/ns. 16. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1V/ns in single ended mode. 17. tDS and tDH (data setup and hold) derating 1) Input waveform timing is referenced from the input signal crossing at the VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test. 2) Input waveform timing is referenced from the input signal crossing at the VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test.
tDS, tDH Derating Values of gDDR2-550 (ALL units in `ps', Note 1 applies to entire Table) DQS,DQS Differential Slew Rate 4.0 V/ns tDS 2.0 1.5 1.0 DQ Slew rate V/ns 0.9 0.8 0.7 0.6 0.5 0.4 125 83 0 45 21 0 3.0 V/ns 125 83 0 -11 45 21 0 -14 2.0 V/ns 125 83 0 -11 -25 45 21 0 -14 -31 1.8 V/ns 95 12 1 -13 -31 33 12 -2 -19 -42 1.6 V/ns 24 13 -1 -19 -43 24 10 -7 -30 -59 1.4V/ns 25 11 -7 -31 -74 22 5 -18 -47 -89 1.2V/ns 23 5 -19 -62 -127 17 -6 -35 -77 -140 1.0V/ns 17 -7 -50 -115 6 -23 -65 -128 0.8V/ns tDH -11 -53 -116 5 -38 -103 tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS
tDS, tDH Derating Values for gDDR2-600/700/800 (ALL units in `ps', Note 1 applies to entire Table) DQS,DQS Differential Slew Rate 4.0 V/ns tDS 2.0 1.5 1.0 DQ Slew rate V/ns 0.9 0.8 0.7 0.6 0.5 0.4 100 67 0 tDH 45 21 0 3.0 V/ns tDS 100 67 0 -5 tDH 45 21 0 -14 2.0 V/ns tDS 100 67 0 -5 -13 tDH 45 21 0 -14 -31 1.8 V/ns tDS 79 12 7 -1 -10 tDH 33 12 -2 -19 -42 1.6 V/ns tDS 24 19 11 2 -10 tDH 24 10 -7 -30 -59 1.4V/ns tDS 31 23 14 2 -24 tDH 22 5 -18 -47 -89 1.2V/ns tDS 35 26 14 -12 -52 tDH 17 -6 -35 -77 -140 1.0V/ns tDS 38 26 0 -40 tDH 6 -23 -65 -128 0.8V/ns tDS 38 12 -28 tDH -11 -53 -116
For all input signals the total tDS (setup time) and tDH(hold time) required is calculated by adding the datasheet tDS(base) and tDH(base) value to the delta tDS and delta tDH derating value respectively. Example : tDS (total setup time) = tDS(base) + delta tDS.
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512M gDDR2 SDRAM
18. tIS and tIH (input setup and hold) derating 1) Input waveform timing is referenced from the input signal crossing at the VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test. 2) Input waveform timing is referenced from the input signal crossing at the VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test. tIS, tIH Derating Values for gDDR2 550 CK,CK Differential Slew Rate 2.0 V/ns tIS 4.0 3.5 3.0 2.5 2.0 1.5 1.0 Command /Adress Slew rate(V/ns) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.25 0.2 0.15 +187 +179 +167 +150 +125 +83 0 -11 -25 -43 -67 -110 -175 -285 -350 -525 -800 tIH +94 +89 +83 +75 +45 +21 0 -14 -31 -54 -83 -125 -188 -292 -375 -500 -708 tIS +217 +209 +197 +180 +155 +113 +30 +19 +5 -13 -37 -80 -145 -255 -320 -495 -770 1.5 V/ns tIH +124 +119 +113 +105 +75 +51 +30 +16 -1 -24 -53 -95 -158 -262 -345 -470 -678 tIS +247 +239 +227 +210 +185 +143 +60 +49 +35 +17 -7 -50 -115 -225 -290 -465 -740 1.0 V/ns tIH +154 +149 +143 +135 +105 +81 +60 +46 +29 +6 -23 -65 -128 -232 -315 -440 -648 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Units Notes
tIS and tIH Derating Values for gDDR2-600, gDDR2-700, gDDR2-800 CK,CK Differential Slew Rate 2.0 V/ns tIS 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.9 Command /Adress Slew rate(V/ns) 0.8 0.7 0.6 0.5 0.4 0.3 0.25 0.2 0.15 0.1 +150 +143 +133 +120 +100 +67 0 -5 -13 -22 -34 -60 -100 -168 -200 -325 -517 -1000 tIH +94 +89 +83 +75 +45 +21 0 -14 -31 -54 -83 -125 -188 -292 -375 -500 -708 -1125 tIS +180 +173 +163 +150 +130 +97 +30 +25 +17 +8 -4 -30 -70 -138 -170 -295 -487 -970 1.5 V/ns tIH +124 +119 +113 +105 +75 +51 +30 +16 -1 -24 -53 -95 -158 -262 -345 -470 -678 -1095 tIS +210 +203 +193 +180 +160 +127 +60 +55 +47 +38 +26 0 -40 -108 -140 -265 -457 -940 1.0 V/ns tIH +154 +149 +143 +135 +105 +81 +60 +46 29 +6 -23 -65 -128 -232 -315 -440 -648 -1065 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Units Notes
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512M gDDR2 SDRAM
19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 20. MIN ( tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). For example, tCL and tCH are = 50% of the period, less the half period jitter ( tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk ( tJIT(crosstalk)) into the clock traces. 21. tQH = tHP - tQHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock low ( tCH, tCL). tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 22. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS / DQS and associated DQ in any given cycle. 23. tDAL = (nWR) + ( tRP/tCK) : For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the application clock period. nWR refers to the tWR parameter stored in the MRS. Example: For gDDR533 at t CK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks =4 +(4)clocks=8clocks. 24. The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock frequency change during precharge power-down, a specific procedure is required as described in gDDR2 device operation 25. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND. 26. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. 27. tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) . Following figure shows a method to calculate the point when device is no longer driving (tHZ), or begins driving (tLZ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. 28. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). Following figure shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. These notes are referenced to the "Timing parameters by speed grade" tables for gDDR2-550/600/700 and gDDR2-800.
VOH + x mV VOH + 2x mV tHZ tRPST end point T2 T1 VOL + 2x mV VOL + x mV
VTT + 2x mV VTT + x mV tLZ tRPRE begin point VTT - x mV VTT - 2x mV T1 T2
tHZ,tRPST end point = 2*T1-T2
tLZ,tRPRE begin point = 2*T1-T2

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512M gDDR2 SDRAM
29. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. 30. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIH(dc) level to the differential data strobe crosspoint for a rising signal and VIL(dc) to the differential data strobe crosspoint for a falling signal applied to the device under test. Differential Input waveform timing
DQS DQS
tDS
tDH
tDS
tDH
VDDQ VIH(AC) min VIH(DC) min VREF VIL(DC) max VIL(AC) max VSS

31. Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac) for a falling signal applied to the device under test. 32. Input waveform timing is referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal applied to the device under test.
CK CK
tIS
tIH
tIS
tIH
VDDQ VIH(AC) min VIH(DC) min VREF VIL(DC) max VIL(AC) max VSS
33. tWTR is at lease two clocks (2 * tCK) independent of operation frequency.
34. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test. The DQS signal must be monotonic between Vil(dc)max and Vih(dc)min. 35. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of its transition for a rising signal, and from the input signal crossing at the VIL(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be monotonic between Vil(dc)max and Vih(dc)min. 36. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registeration. Thus, after any cKE transition, CKE may not transitioin from its valid level during the time period of tIS + 2*tCK + tIH.
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512M gDDR2 SDRAM
Device Operation & Timing Diagram
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Functional Description Simplified State Diagram
Initialization Sequence CKEL OCD calibration SRF PR Setting MRS EMRS (E)MRS Idle All banks precharged ACT CKEL CKEH Precharge Power Down REF
512M gDDR2 SDRAM
Self Refreshing CKEH
Refreshing
CKEL
CKEL CKEL Active Power Down CKEL
Activating
CKEL Automatic Sequence Command Sequence
CKEH Bank Active
Write
Write WRA Writing RDA Read Write
Read Read
Reading
WRA WRA Writing with Autoprecharge PR, PRA PR, PRA PR, PRA RDA
RDA
Reading with Autoprecharge
Precharging
CKEL = CKE low, enter Power Down CKEH = CKE high, exit Power Down, exit Self Refresh ACT = Activate WR(A) = Write (with Autoprecharge) RD(A) = Read (with Autoprecharge) PR(A) = Precharge (All) (E)MRS = (Extended) Mode Register Set SRF = Enter Self Refresh REF = Refresh
Note : Use caution with this diagram. It is indented to provide a floorplan of the possible state transitions and the commands to control them, not all details. In particular situations involving more than one bank, enabling/disabling on-die termination, Power Down entry/ exit - among other things - are not captured in full detail.
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Basic Functionality
512M gDDR2 SDRAM
Read and write accesses to the gDDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the active command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access and to determine if the auto precharge command is to be issued. Prior to normal operation, the gDDR2 SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.
Power up and Initialization
gDDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation.
Power-up and Initialization Sequence
The following sequence is required for POWER UP and Initialization. 1. Apply power and attempt to maintain CKE below 0.2*VDDQ and ODT*1 at a low state (all other inputs may be undefined.) The power voltage ramps are without any slope reversal, ramp time must be no greater than 20mS; and during the ramp, VDD>VDDL>VDDQ and VDD-VDDQ<0.3 volts. - VDD*2, VDDL*2 and VDDQ are driven from a single power converter output, AND - VTT is limited to 0.95 V max, AND
- Vref tracks VDDQ/2.
or - Apply VDD*2 before or at the same time as VDDL. - Apply VDDL*2 before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VTT & VREF.
at least one of these two sets of conditions must be met. 2. Start clock and maintain stable condition. 3. For the minimum of 200s after stable power and clock(CK, CK), then apply NOP or deselect & take CKE high. 4. Wait minimum of 400ns then issue precharge all command. NOP or deselect applied during 400ns period. 5. Issue EMRS(2) command. (To issue EMRS(2) command, provide "Low" to BA0, "High" to BA1.) 6. Issue EMRS(3) command. (To issue EMRS(3) command, provide "High" to BA0 and BA1.) 7. Issue EMRS to enable DLL. (To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and "Low" to BA1 and A12.) 8. Issue a Mode Register Set command for "DLL reset"*2. (To issue DLL reset command, provide "High" to A8 and "Low" to BA0-1) 9. Issue precharge all command. 10. Issue 2 or more auto-refresh commands. 11. Issue a mode register set command with low to A8 to initialize device operation. (i.e. to program operating parameters without resetting the DLL. 12. At least 200 clocks after step 8, execute OCD Calibration ( Off Chip Driver impedance adjustment ). If OCD calibration is not used, EMRS OCD Default command (A9=A8= A7=1) followed by EMRS OCD Calibration Mode Exit command (A9=A8=A7=0) must be issued with other operating parameters of EMRS. 13. The gDDR2 SDRAM is now ready for normal operation.
*1) To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin. *2) If DC voltage level of VDDL or VDD is intentionally changed during normal operation, (for example, for the purpose of VDD corner test, or power saving) "DLL Reset" must be executed.
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Initialization Sequence after Power Up
tCH tCL
512M gDDR2 SDRAM
CK /CK CKE ODT Command
NOP PRE ALL 400ns tRP EMRS MRS PRE ALL tMRD tRP REF REF tRFC min. 200 Cycle OCD Default OCD CAL. MODE EXIT tRFC MRS EMRS EMRS ANY CMD tOIT VIH(ac) tIS
tMRD
tMRD
Follow OCD Flowchart
DLL ENABLE
DLL RESET
Programming the Mode Register
For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time(tWR) are user defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, driver impedance, additive CAS latency, ODT(On Die Termination), single-ended strobe, and OCD(off chip driver impedance adjustment) are also user defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register(MR) or Extended Mode Registers(EMR(#)) can be altered by re-executing the MRS and EMRS Commands. If the user chooses to modify only a subset of the MRS or EMRS variables, all variables must be redefined when the MRS or EMRS commands are issued. MRS, EMRS and Reset DLL do not affect array contents, which means reinitialization including those can be executed any time after power-up without affecting array contents.
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gDDR2 SDRAM Mode Register Set (MRS)
512M gDDR2 SDRAM
The mode register stores the data for controlling the various operating modes of gDDR2 SDRAM. It controls CAS latency, burst length, burst sequence, test mode, DLL reset, tWR and various vendor specific options to make gDDR2 SDRAM useful for various applications. The default value of the mode register is not defined, therefore the mode register must be written after power-up for proper operation. The mode register is written by asserting low on CS, RAS, CAS, WE, BA0 and BA1, while controlling the state of address pins A0 ~ A15. The gDDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register. The mode register set command cycle time (tMRD) is required to complete the write operation to the mode register. The mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. The mode register is divided into various fields depending on functionality. Burst length is defined by A0 ~ A2 with options of 4 and 8 bit burst lengths. The burst length decodes are compatible with gDDR SDRAM. Burst address sequence type is defined by A3, CAS latency is defined by A4 ~ A6. The gDDR2 doesn't support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Write recovery time tWR is defined by A9 ~ A11. Refer to the table for specific codes.
BA1 0
BA0 0
A12 PD
A11
A10
A9
A8 DLL
A7 TM
A6
A5 CAS Latency
A4
A3 BT
A2
A1 Burst Length
A0
Address Bus Mode Register
tWR*1
Test Mode
A12 0 1 BA1 0 0 1 1 Active Power Down exit time Fast exit (use tXARD) Slow exit (use tXARDS) BA0 0 1 0 1 MRS Mode MRS EMRS (1) EMRS (2) : Reserved EMRS (3) : Reserved A7 0 1 mode Normal Test
Burst Type
A3 0 1 Type Sequential Interleave
DLL
A8 0 1 DLL Reset No Yes
Burst Length
A2 0 0 A1 1 1 A0 0 1 Burst Length 4 8
Write Recovery for Auto Precharge
A11 0 0 0 0 1 1 1 1 A10 0 0 1 1 0 0 1 1 A9 0 1 0 1 0 1 0 1 MRS Select Reserved Reserved 3 4 5 Reserved Reserved Reserved
CAS Latency
A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserved Reserved Reserved 3 4 5 6 Reserved
*1 : WR(write recovery for autoprecharge) min is determined by tCK max and WR max is determined by tCK min. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up a non-integer value to the next integer (WR[cycles] = tWR(ns)/tCK(ns)). The mode register must be programmed to this value. This is also used with tRP to determine tDAL.
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gDDR2 SDRAM Extended Mode Register Set
512M gDDR2 SDRAM
EMRS(1) The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, ODT value selection and additive latency. The default value of the extended mode register is not defined, therefore the extended mode register must be written after power-up for proper operation. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0, while controlling the states of address pins A0 ~ A12. The gDDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register. The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register. Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. A0 is used for DLL enable or disable. A1 is used for enabling a half strength data-output driver. A3~A5 determines the additive latency, A2 and A6 are used for ODT value selection, A7~A9 are used for OCD control, A10 is used for DQS# disable. DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering self refresh operation and is automatically reenabled upon exit of self refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters.
EMRS(2) The extended mode register(2) controls refresh related features. The default value of the extended mode register(2) is not defined, therefore the extended mode register(2) must be written after power-up for proper operation. The extended mode register(2) is written by asserting low on CS, RAS, CAS, WE, high on BA1 and low on BA0, while controlling the ststes of address pins A0 ~ A15. The gDDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register(2). The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register(2). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state.
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EMRS (1) Programming BA1 0 BA0 1 A12 Qoff A11 0 A10 DQS A9 A8 OCD Program A7 A6 Rtt A5
512M gDDR2 SDRAM
A4
A3
A2 Rtt
A1 D.I.C
A0 DLL
Additive Latency
BA1 0 0 1 1
BA0 0 1 0 1
MRS mode MRS EMRS(1) EMRS(2): Reserved EMRS(3): Reserved
A10 0 1
DQS Enable Disable
A6 0 0 1 1
A2 0 1 0 1
Rtt (NOMINAL) ODT Disabled 75 ohm 150 ohm 50 ohm
A0 0 1
DLL Enable Enable Disable
A10 (DQS Enable) 0 (Enable) 1 (Disable) A12 0 1 Qoff (Optional)a Output buffer enabled Output buffer disabled A9 0 0 0 1 1
Strobe Function Matrix DQS DQS DQS A8 0 0 1 0 1 A7 0 1 0 0 1 DQS DQS Hi-z OCD Calibration Program OCD Calibration mode exit; maintain setting Drive(1) Drive(0) Adjust modea OCD Calibration default
b
A1 0 1
Output Driver Impedance Control Normal Weak
Driver Size 100% 60%
A5 0 0 0 0 1 1 1 1
A4 0 0 1 1 0 0 1 1
A3 0 1 0 1 0 1 0 1
Additive Latency 0 1 2 3 4 5a Reserved Reserved
a. Outputs disabled - DQs, DQSs, DQSs . This feature is used in conjunction with dimm IDD meaurements when IDDQ is not desired to be included.
a: When Adjust mode is issued, AL from previously set value must be applied. b: After setting to default, OCD mode needs to be exited by setting A9-A7 to 000. Refer to the following 3.2.2.3 section for detailed information.
a. AL 5 option is available only for 256Mb gDDR2.
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EMRS (2) Programming
512M gDDR2 SDRAM
BA1 1
BA0 0*1
A12
A11
A10 0*1
A9
A8
A7 SRF
A6
A5 0*1
A4
A3
A2
A1 PSAR*2
A0
Address Field
Extended Mode Register(2)
BA1 0 0 1 1
BA0 0 1 0 1
MRS mode MRS EMRS(1) EMRS(2) EMRS(3): Reserved
A7 1 0
High Temperature Self-Refresh Rate Enable Enable Disable
A2 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1
A0 Partial Array Self Refresh for 4 Banks 0 1 0 1 0 1 0 1 Full array Half Array(BA[1:0]=00&01) Quarter Array(BA[1:0]=00) Not defined 3/4 array(BA[1:0]=01, 10&11) Half array(BA[1:0]=10&11) Quarter array(BA[1:0]=11) Not defined
*1 : The rest bits in EMRS(2) is reserved for future use and all bits except A0, A1, A2, A7and BA0, BA1, must be programmed to 0 when setting the mode register during initialization. . *2 : If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be loast if self refresh is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued. PASR is supported from the device of 90nm technology(512Mb C-die).
EMRS (3) Programming : Reserved*1
BA1 1
BA0 1
A12
A11
A10
A9
A8
A7
A6 0*1
A5
A4
A3
A2
A1
A0
Address Field
Extended Mode Register(3)
*1 : All bits in EMRS(3) except BA0 and BA1 are reserved for future use and must be programmed to 0 when setting the mode register during initialization.
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K4N51163QC-ZC
Off-Chip Driver (OCD) Impedance Adjustment
512M gDDR2 SDRAM
gDDR2 SDRAM supports driver calibration feature and the flow chart below is an example of sequence. Every calibration mode command should be followed by "OCD calibration mode exit" before any other command being issued. MRS should be set before entering OCD impedance adjustment and ODT (On Die Termination) should be carefully controlled depending on system environment.
MRS shoud be set before entering OCD impedance adjustment and ODT should be carefully controlled depending on system environment
Start EMRS: OCD calibration mode exit
EMRS: Drive(1) DQ & DQS High; DQS Low
EMRS: Drive(0) DQ & DQS Low; DQS High
ALL OK Test Need Calibration EMRS: OCD calibration mode exit
ALL OK Test Need Calibration EMRS: OCD calibration mode exit
EMRS : Enter Adjust Mode
EMRS : Enter Adjust Mode
BL=4 code input to all DQs Inc, Dec, or NOP
BL=4 code input to all DQs Inc, Dec, or NOP
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
End
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Rev 1.5 Oct. 2005
K4N51163QC-ZC
Extended Mode Register Set for OCD impedance adjustment
512M gDDR2 SDRAM
OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are driven out by gDDR2 SDRAM and drive of DQS is dependent on EMRS bit enabling DQS operation. In Drive(1) mode, all DQ, DQS signals are driven high and all DQS signals are driven low. In drive(0) mode, all DQ, DQS signals are driven low and all DQS signals are driven high. In adjust mode, BL = 4 of operation code data must be used. In case of OCD calibration default, output driver characteristics have a nominal impedance value of 18 ohms during nominal temperature and voltage conditions. Output driver characteristics for OCD calibration default are specified in section 6. OCD applies only to normal full strength output drive setting defined by EMRS(1) and if half strength is set, OCD default output driver characteristics are not applicable. When OCD calibration adjust mode is used, OCD default output driver characteristics are not applicable. After OCD calibration is completed or driver strength is set to default, subsequent EMRS commands not intended to adjust OCD characteristics must specify A9-A7 as '000' in order to maintain the default or calibrated value.
Off- Chip-Driver program A9 0 0 0 1 1 A8 0 0 1 0 1 A7 0 1 0 0 1 Operation OCD calibration mode exit Drive(1) DQ, DQS high and DQS low Drive(0) DQ, DQS low and DQS high Adjust mode OCD calibration default
OCD impedance adjust To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a 4bit burst code to gDDR2 SDRAM as in the following table. For this operation, Burst Length has to be set to BL = 4 via MRS command before activating OCD and controllers must drive this burst code to all DQs at the same time. DT0 in the following table means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all gDDR2 SDRAM DQs simultaneously and after OCD calibration, all DQs of a given gDDR2 SDRAM will be adjusted to the same driver strength setting. The maximum step count for adjustment is 16 and when the limit is reached, further increment or decrement code has no effect. The default setting may be any step within the 16 step range. When Adjust mode command is issued, AL from previously set value must be applied.
Off- Chip-Driver program 4bit burst code inputs to all DQs DT0 0 0 0 0 1 0 0 1 1 DT1 0 0 0 1 0 1 1 0 0 DT2 0 0 1 0 0 0 1 0 1 DT3 0 1 0 0 0 1 0 1 0 Pull-up driver strength NOP (No operation) Increase by 1 step Decrease by 1 step NOP NOP Increase by 1 step Decrease by 1 step Increase by 1 step Decrease by 1 step Reserved Operation Pull-down driver strength NOP (No operation) NOP NOP Increase by 1 step Decrease by 1 step Increase by 1 step Increase by 1 step Decrease by 1 step Decrease by 1 step
Other Combinations
For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1 clocks and tDS/tDH should be met as the following timing diagram. For input data pattern for adjustment, DT0 - DT3 is a fixed order and "not affected by MRS addressing mode (ie. sequential or interleave).
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OCD adjust mode
CMD CK CK WL DQS_in
tDS tDH
VIH(AC) VIL(AC) VIH(DC) VIL(DC)
512M gDDR2 SDRAM
OCD calibration mode exit NOP NOP NOP NOP EMRS NOP
EMRS
NOP
DQS
WR
DQ_in DM
DT0
DT1
DT2
DT3
Drive Mode Drive mode, both Drive(1) and Drive(0), is used for controllers to measure gDDR2 SDRAM Driver impedance. In this mode, all outputs are driven out tOIT after "enter drive mode" command and all output drivers are turned-off tOIT after "OCD calibration mode exit" command as the following timing diagram.
Enter Drive mode CMD EMRS NOP NOP NOP OCD calibration mode exit EMRS
CK CK Hi-Z DQS DQS DQs high for Drive(1) DQ DQs low for Drive(0) DQS high & DQS low for Drive(1), DQS low & DQS high for Drive(0) Hi-Z
tOIT
tOIT
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Rev 1.5 Oct. 2005
K4N51163QC-ZC
ODT (On Die Termination)
512M gDDR2 SDRAM
On Die Termination (ODT) is a feature that allows a DRAM to turn on/off termination resistance. For x16 configuration ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices. The ODT function is supported for ACTIVE and STANDBY modes, and turned off and not supported in SELF REFRESH mode. Functional Representation of ODT
VDDQ sw1 VDDQ VDDQ Switch (sw1, sw2, sw3) is enabled by ODT pin. Selection among sw1, sw2 and sw3 is determined by "Rtt (nominal)" in EMRS Termination included on all DQs, DM, DQS, DQS, RDQS, and RDQS pins.
sw2 Rval2
sw3 Rval3
Rval1 DRAM Input Buffer Rval1
Input Pin Rval2 Rval3
sw1 VSSQ
sw2 VSSQ
sw3 VSSQ
ODT DC Electrical Characteristics Parameter/Condition Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 ohm Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 ohm Rtt mismatch tolerance between any pull-up/pull-down pair Symbol Rtt1(eff) Rtt2(eff) Rtt(mis) Min 60 120 -3.75 Nom 75 150 Max 90 180 +3.75 Units ohm ohm % Notes 1 1 1
Note 1: Test condition for Rtt measurements Measurement Definition for Rtt(eff): Apply VIH (AC) and VIL (AC) to test pin separately, then measure current I(VIH (AC)) and I( VIL (AC)) respectively. VIH (AC), VIL (AC), and VDDQ values defined in SSTL_18 VIH (AC) - VIL (AC)
Rtt(eff) =
I(VIH (AC)) - I(VIL (AC))
delta VM =
2 x Vm VDDQ
-1
x 100%
Measurement Definition for VM : Measure voltage (VM) at test pin (midpoint) with no load.
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Rev 1.5 Oct. 2005
K4N51163QC-ZC
ODT timing for active/standby mode T0 CK CK T1 T2 T3 T4
512M gDDR2 SDRAM
T5
T6
CKE tIS ODT
VIH(AC)
tIS
VIL(AC)
tAOND Internal Term Res. tAON,min
tAOFD RTT tAOF,min tAON,max tAOF,max
ODT timing for powerdown mode T0 CK CK T1 T2 T3 T4 T5 T6
CKE tIS ODT
VIH(AC)
tIS
VIL(AC)
tAOFPD,max RTT
tAOFPD,min Internal Term Res. tAONPD,min tAONPD,max
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Rev 1.5 Oct. 2005
K4N51163QC-ZC
ODT timing mode switch at entering power down mode T-5 CK CK tANPD tIS CKE Entering Slow Exit Active Power Down Mode or Precharge Power Down Mode. tIS ODT
VIL(AC)
512M gDDR2 SDRAM
T-4 T-3 T-2 T-1 T0 T1 T2 T3 T4
tAOFD Internal Term Res. tIS ODT
VIL(AC)
Active & Standby mode timings to be applied.
RTT
tAOFPDmax Internal Term Res. tIS ODT
VIH(AC)
Power Down mode timings to be applied.
RTT
tAOND Internal Term Res. tIS ODT
VIH(AC)
Active & Standby mode timings to be applied. RTT
tAONPDmax Internal Term Res. RTT
Power Down mode timings to be applied.
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Rev 1.5 Oct. 2005
K4N51163QC-ZC
ODT timing mode switch at exiting power down mode T0 CK CK tIS CKE
VIH(AC)
512M gDDR2 SDRAM
T1
T4
T5
T6
T7
T8
T9
T10
T11
tAXPD
Exiting from Slow Active Power Down Mode or Precharge Power Down Mode. tIS Active & Standby mode timings to be applied. ODT
VIL(AC)
tAOFD Internal Term Res. tIS
RTT
Power Down mode timings to be applied.
ODT
VIL(AC)
tAOFPDmax Internal Term Res. RTT
tIS
Active & Standby mode timings to be applied. ODT
VIH(AC)
tAOND Internal Term Res. tIS Power Down mode timings to be applied. ODT
VIH(AC)
RTT
tAONPDmax Internal Term Res. RTT
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K4N51163QC-ZC
Bank Activate Command
512M gDDR2 SDRAM
Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in gDDR2 SDRAM. In this operation, the gDDR2 SDRAM allows a CAS read or write command to be issued immediately after the RAS bank activate command (or any time during the RAS-CAS-delay time, tRCD, period). The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of AL and the CAS latency (CL). Therefore if a user chooses to issue a R/W command before the tRCDmin, then AL (greater than 0) must be written into the EMR(1). The Write Latency (WL) is always defined as RL - 1 (read latency -1) where read latency is defined as the sum of additive latency plus CAS latency (RL=AL+CL). Read or Write operations using AL allow seamless bursts (refer to seamless operation timing diagram examples in Read burst and Write burst section)
Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2
T0 CK / CK
T1
T2
T3
Tn
..........
Tn+1
Tn+2
Tn+3
Internal RAS-CAS delay (>= tRCDmin)
ADDRESS
Bank A Row Addr. RCD =1
Bank A Col. Addr.
Bank B Row Addr.
Bank B Col. Addr.
. . . . . . . . . Bank A . Addr.
Bank B Addr.
Bank A Row Addr.
CAS-CAS delay time (tCCD) additive latency delay (AL)
Read Begins
RAS - RAS delay time (>= tRRD) Bank A Activate Post CAS Read A Bank B Activate Bank Active (>= tRAS) Post CAS Read B . . . . . . . . . Bank A . Precharge Bank B Precharge Bank A Active
COMMAND
: "H" or "L"
Bank Precharge time (>= tRP) RAS Cycle time (>= tRC)
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high, CS and CAS low at the clock's rising edge. WE must also be defined at this time to determine whether the access cycle is a read operation (WE high) or a write operation (WE low). The DDR2 SDRAM provides a fast column access operation. A single Read or Write Command will initiate a serial read or write operation on successive clock cycles. The boundary of the burst cycle is strictly restricted to specific segments of the page length. For example, the 32Mbit x 4 I/O x 4 Bank chip has a page length of 2048 bits (defined by CA0-CA9, CA11). The page length of 2048 is divided into 512 or 256 uniquely addressable boundary segments depending on burst length, 512 for 4 bit burst, 256 for 8 bit burst respectively. A 4-bit or 8 bit burst operation will occur entirely within one of the 512 or 256 groups beginning with the column address supplied to the device during the Read or Write Command (CA0-CA9, CA11). The second, third and fourth access will also occur within this group segment, however, the burst order is a function of the starting address, and the burst sequence. A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. However, in case of BL = 8 setting, two cases of interrupt by a new burst access are allowed, one reads interrupted by a read, the other writes interrupted by a write with 4 bit burst boundry respectively. The minimum CAS to CAS delay is defined by tCCD, and is a minimum of 2 clocks for read or write cycles.
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K4N51163QC-ZC
Posted CAS
512M gDDR2 SDRAM
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst length. gDDR2 SDRAM supports 4 bit burst and 8 bit burst modes only. For 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (A3) of the MRS, which is similar to the DDR SDRAM operation. Seamless burst read or write operations are supported. Unlike DDR devices, interruption of a burst read or write cycle during BL = 4 mode operation is prohibited. However in case of BL = 8 mode, interruption of a burst read or write operation is limited to two cases, reads interrupted by a read, or writes interrupted by a write. Therefore the Burst Stop command is not supported on gDDR2 SDRAM devices.
Examples of posted CAS operation Example 1 Read followed by a write to the same bank [AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4] -1 CK/CK
Active Read A-Bank A-Bank AL = 2 > = tRCD Write A-Bank CL = 3
0
1
2
3
4
5
6
7
8
9
10
11
12
CMD DQS/DQS DQ
WL = RL -1 = 4
RL = AL + CL = 5 > = tRAC
Dout0 Dout1 Dout2 Dout3
Din0Din1Din2Din3
Example 2
Read followed by a write to the same bank [AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2]
-1 CK/CK
0
1
2
3
4
5
6
7
8
9
10
11
12
AL = 0
CMD DQS/DQS DQ
Active A-Bank
Read A-Bank CL = 3
Write A-Bank WL = RL -1 = 2
> = tRCD RL = AL + CL = 3 > = tRAC
Dout0 Dout1 Dout2 Dout3
Din0Din1Din2Din3
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Rev 1.5 Oct. 2005
K4N51163QC-ZC
Burst Mode Operation
512M gDDR2 SDRAM
The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is driven low 1 clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined by the Mode Register Set (MRS), similar to the existing SDR and DDR SDRAMs. The AL is defined by the Extended Mode Register Set (1)(EMRS(1)). gDDR2 SDRAM pin timings are specified for either single ended mode or differen-tial mode depending on the setting of the EMRS "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the gDDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 ohm to 10 Kohm resis-tor to insure proper operation.
Burst Length and Sequence BL = 4 Burst Length Starting Address (A1 A0) 00 4 01 10 11 BL = 8 Burst Length Starting Address (A2 A1 A0) 000 001 010 8 011 100 101 110 111 Sequential Addressing (decimal) 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2 Interleave Addressing (decimal) 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 Sequential Addressing (decimal) 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 Interleave Addressing (decimal) 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0
Note : Page length is a function of I/O organization and column addressin
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Rev 1.5 Oct. 2005
K4N51163QC-ZC
Burst Read Command
512M gDDR2 SDRAM
The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus one and is equal to (AL + CL -1). A data strobe signal (DQS) should be driven low (preamble) one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for write cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed, which is 4 or 8 bit burst. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery time (WR). gDDR2 SDRAM pin timings are specified for either single ended mode or differen-tial mode depending on the setting of the EMRS "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the gDDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 ohm to 10K ohm resistor to insure proper operation.
tCH CK tCL
CK
CK
DQS
DQS
DQS tRPRE tRPST Q tDQSQmax tQH Q Q tDQSQmax tQH Q
DQ
Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4) T0 CK/CK T1 T2 T3 T4 T5 T6 T7 T8
CMD
Posted CAS READ A
NOP
NOP
NOP
NOP
NOP =< tDQSCK
NOP
NOP
NOP
DQS
AL = 2 RL = 5 CL =3
DOUTA0 DOUTA1 DOUTA2 DOUTA3
DQs
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Rev 1.5 Oct. 2005
K4N51163QC-ZC
Burst Read Operation: RL = 3 (AL = 0 and CL = 3, BL = 8) T0 CK/CK T1 T2 T3 T4 T5 T6
512M gDDR2 SDRAM
T7 T8
CMD
CAS READ A
NOP
NOP
NOP =< tDQSCK
NOP
NOP
NOP
NOP
NOP
DQS
CL =3 RL = 3
DQs
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A4
DOUT A5
DOUT A6
DOUT A7
Burst Read followed by Burst Write: RL = 5, WL = (RL-1) = 4, BL = 4 T0 CK/CK T1 Tn-1 Tn Tn+1 Tn+2 Tn+3 Tn+4 Tn+5
CMD
Post CAS READ A
NOP
NOP
Post CAS NOP WRITE A tRTW (Read to Write turn around time)
NOP
NOP
NOP
NOP
DQS
RL =5 WL = RL - 1 = 4
DQ's
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DIN A0
DIN A1
DIN A2
DIN A3
The minimum time from the burst read command to the burst write command is defined by a read-to-write-turn-around-time, which is 4 clocks in case of BL = 4 operation, 6 clocks in case of BL = 8 operation.
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K4N51163QC-ZC
512M gDDR2 SDRAM
T0 CK/CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
Post CAS READ A0
NOP
Post CAS READ A4
NOP
NOP
NOP
NOP
NOP
NOP
DQS
AL = 2 RL = 5 CL =3
DQs
DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A4 DOUT A5 DOUT A6
The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4 operation, and every 4 clock for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated.
Burst read can only be interrupted by another read with 4 bit burst boundary. Any other case of read interrupt is not allowed. Read Burst Interrupt Timing Example: (CL=3, AL=0, RL=3, BL=8)
CK/CK
CMD
Read A
NOP
Read B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS/DQS DQs A0 A1 A2 A3 B0 B1 B2 B3 B4 B5 B6 B7
Notes: 1. Read burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited. 2. Read burst of 8 can only be interrupted by another Read command. Read burst interruption by Write command or Precharge command is prohibited. 3. Read burst interrupt must occur exactly two clocks after previous Read command. Any other Read burst interrupt timings are prohibited. 4. Read burst interruption is allowed to any bank inside DRAM. 5. Read burst with Auto Precharge enabled is not allowed to interrupt. 6. Read burst interruption is allowed by another Read with Auto Precharge command. 7. All command timings are referenced to burst length set in the mode register. They are not referenced to actual burst. For example, Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt).
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K4N51163QC-ZC
Burst Write Operation
512M gDDR2 SDRAM
The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus one and is equal to (AL + CL -1);and is the number of clocks of delay that are required from the time the write command is registered to the clock edge associated to the first DQS strobe. A data strobe signal (DQS) should be driven low (preamble) one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for each positive DQS transition to its associated clock edge during write cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed, which is 4 or 8 bit burst. When t he burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery time (WR). DDR2 SDRAM pin timings are specified for either single ended mode or differen-tial mode depending on the setting of the EMRS "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at the specified AC/DC levels. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 ohm to 10K ohm resistor to insure proper operation.
DQS
tDQSH
tDQSL
DQS/ DQS
DQS tWPRE
VIH(ac) VIL(ac)
tWPST
DQ
D
D
VIH(dc) VIL(dc)
D
D tDH DMin
VIL(dc) VIH(dc)
tDS
tDS DMin
VIH(ac) VIL(ac)
tDH DMin
DM
DMin
Burst Write Operation: RL = 5, WL = 4, tWR = 3 (AL=2, CL=3), BL = 4 T0 CK/CK T1 T2 T3 T4 T5 T6 T7 Tn
CMD
Posted CAS WRITE A
NOP
NOP
NOP
NOP < = tDQSS
NOP
NOP
NOP
Precharge
Completion of the Burst Write
DQS
WL = RL - 1 = 4 > = WR DIN A0 DIN A1 DIN A2 DIN A3
DQs
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Rev 1.5 Oct. 2005
K4N51163QC-ZC
Burst Write Operation: RL = 3, WL = 2, tWR = 2 (AL=0, CL=3), BL = 4 T0 CK/CK T1 T2 T3 T4 T5 T6
512M gDDR2 SDRAM
T7 Tn
CMD
CAS WRITE A
NOP
NOP < = tDQSS
NOP
NOP
NOP
Precharge
NOP
Completion of the Burst Write
Bank A Activate
DQS
WL = RL - 1 = 2 > = WR
DIN A0 DIN A1 DIN A2 DIN A3
> = tRP
DQs
Burst Write followed by Burst Read: RL = 5 (AL=2, CL=3), WL = 4, tWTR = 2, BL = 4 T0 CK/CK
Write to Read = CL - 1 + BL/2 + tWTR
T1
T2
T3
T4
T5
T6
T7
T8
T9
CMD
NOP
NOP
NOP
NOP
Post CAS READ A
NOP
NOP
NOP
NOP
DQS
WL = RL - 1 = 4 AL = 2 RL =5 > = tWTR CL = 3
DQ
DOUT A0 DOUT A1 DOUT A2 DOUT A3
The minimum number of clock from the burst write command to the burst read command is [CL - 1 + BL/2 + tWTR]. This tWTR is not a write recovery time (tWR) but the time required to transfer the 4bit write data from the input buffer into sense amplifiers in the array. tWTR is defined in AC spec table of this data sheet.
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Seamless Burst Write Operation: RL = 5, WL = 4, BL=4 T0 CK/CK T1 T2 T3 T4 T5 T6
512M gDDR2 SDRAM
T7
T8
CMD
Post CAS WRITE A0
NOP
Post CAS WRITE A1
NOP
NOP
NOP
NOP
NOP
NOP
DQS
WL = RL - 1 = 4
DQ's
DIN A0 DIN A1 DIN A2 DIN A3 DIN A0 DIN A1 DIN A2 DIN A3
The seamless burst write operation is supported by enabling a write command every other clock for BL = 4 operation, every four clocks for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated.
Writes intrrupted by a write Burst write can only be interrupted by another write with 4 bit burst boundary. Any other case of write interrupt is not allowed. Write Burst Interrupt Timing Example: (CL=3, AL=0, RL=3, WL=2, BL=8)
CK/CK
CMD
NOP
Write A
NOP
Write B
NOP
NOP
NOP
NOP
NOP
NOP
DQS/DQS
DQs
A0
A1
A2
A3
B0
B1
B2
B3
B4
B5
B6
B7
Notes: 1. Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited. 2. Write burst of 8 can only be interrupted by another Write command. Write burst interruption by Read command or Precharge command is prohibited. 3. Write burst interrupt must occur exactly two clocks after previous Write command. Any other Write burst interrupt timings are prohibited. 4. Write burst interruption is allowed to any bank inside DRAM. 5. Write burst with Auto Precharge enabled is not allowed to interrupt. 6. Write burst interruption is allowed by another Write with Auto Precharge command. 7. All command timings are referenced to burst length set in the mode register. They are not referenced to actual burst. For example, minimum Write to Precharge timing is WL+BL/2+tWR where tWR starts with the rising clock after the un-interrupted burst end and not from the end of actual burst end.
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Write data mask
512M gDDR2 SDRAM
One write data mask (DM) pin for each 8 data bits (DQ) will be supported on gDDR2 SDRAMs, Consistent with the implementation on gDDR SDRAMs. It has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. DM of x16 bit organization is not used during read cycles. Data Mask Timing
DQS/ DQS DQ DM
VIH(ac) VIH(dc) VIL(ac) VIL(dc) VIH(ac) VIH(dc) VIL(ac) VIL(dc)
tDS tDH
tDS tDH
Data Mask Function, WL=3, AL=0, BL = 4 shown
Case 1 : min tDQSS
CK CK COMMAND DQS/DQS DQ DM Case 2 : max tDQSS DQS/DQS DQ DM tDQSS
Write
tDQSS
tWR
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Precharge Command
512M gDDR2 SDRAM
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank independently or all banks simultaneously. Three address bits A10, BA0 and BA1 for 256Mb are used to define which bank to precharge when the command is issued.
Bank Selection for Precharge by Address Bits
A10 LOW LOW LOW LOW HIGH BA1 LOW LOW HIGH HIGH DON'T CARE BA0 LOW HIGH LOW HIGH DON'T CARE Precharged Bank(s) Bank 0 only Bank 1 only Bank 2 only Bank 3 only All Banks Remarks
Burst Read Operation Followed by Precharge
Minimum Read to precharge command spacing to the same bank = AL + BL/2 clocks. For the earliest possible precharge, the precharge command may be issued on the rising edge which is "Additive latency(AL) + BL/2 clocks" after a Read command. A new bank active (command) may be issued to the same bank after the RAS precharge time (tRP). A precharge command cannot be issued until tRAS is satisfied. The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates the last 4bit prefetch of a Read to Precharge command. This time is called tRTP (Read to Precharge). For BL = 4 this is the time from the actual read (AL after the Read command) to Precharge command. For BL = 8 this is the time from AL + 2 clocks after the Read to the Precharge command.
Example 1: Burst Read Operation Followed by Precharge: RL = 4, AL = 1, CL = 3, BL = 4, tRTP <= 2 clocks T0 CK/CK T1 T2 T3 T4 T5 T6 T7 T8
CMD
Post CAS READ A
NOP AL + BL/2 clks
NOP
Precharge
NOP
NOP
NOP
Bank A Active
NOP
DQS
AL = 1 RL =4 CL = 3 > = tRP
DQ's
> = tRAS > = tRTP
DOUT A0 DOUT A1 DOUT A2 DOUT A3
CL =3
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Example 2: Burst Read Operation Followed by Precharge: RL = 4, AL = 1, CL = 3, BL = 8, tRTP <= 2 clocks
512M gDDR2 SDRAM
T0 CK/CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
Post CAS READ A
NOP
NOP
NOP
NOP
Precharge A
NOP
NOP
NOP
AL + BL/2 clks
DQS
AL = 1 RL =4 CL = 3
DQ's
DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A4 DOUT A5 DOUT A6 DOUT A8
> = tRTP first 4-bit prefetch second 4-bit prefetch
Example 3: Burst Read Operation Followed by Precharge : RL = 5, AL = 2, CL = 3, BL = 4, tRTP <= 2 clocks T0 CK/CK T1 T2 T3 T4 T5 T6 T7 T8
CMD
Posted CAS READ A
NOP
NOP AL + BL/2 clks
NOP
Precharge A
NOP
NOP
Bank A Activate
NOP
DQS
> = tRP AL = 2 RL =5 CL =3
DQ's
> = tRAS > = tRTP
DOUT A0 DOUT A1 DOUT A2 DOUT A3
CL =3
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Example 4: Burst Read Operation Followed by Precharge : RL = 6, AL = 2, CL = 4, BL = 4, tRTP <= 2 clocks T0 CK/CK T1 T2 T3 T4 T5
512M gDDR2 SDRAM
T6
T7
T8
CMD
Post CAS READ A
NOP
NOP AL + BL/2 Clks
NOP
Precharge A
NOP
NOP
Bank A Activate
NOP
DQS
> = tRP AL = 2 RL = 6 CL =4
DQ's
> = tRAS > = tRTP CL =4
DOUT A0 DOUT A1 DOUT A2 DOUT A3
Example 5: Burst Read Operation Followed by Precharge : RL = 4, AL = 0, CL = 4, BL = 8, tRTP > 2 clocks T0 CK/CK T1 T2 T3 T4 T5 T6 T7 T8
CMD
Post CAS READ A
NOP
NOP
NOP
NOP
Precharge A
NOP
NOP
Bank A Activate
AL + 2 Clks + max{tRTP;2 tCK}*
DQS
AL = 0 CL =4 RL = 4 > = tRP
DQ's
> = tRAS > = tRTP
DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A4 DOUT A5 DOUT A6 DOUT A8
first 4-bit prefetch * : rounded to next integer
second 4-bit prefetch
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Burst Write followed by Precharge
512M gDDR2 SDRAM
Minimum Write to Precharge Command spacing to the same bank = WL + BL/2 clks + tWR For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge Command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion of the burst write to the precharge command. No Precharge command should be issued prior to the tWR delay.
Example 1 : Burst Write followed by Precharge: WL = (RL-1) =3, BL=4 T0 CK/CK T1 T2 T3 T4 T5 T6 T7 T8
CMD
Posted CAS WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Precharge A
Completion of the Burst Write
> = tWR
DQS
WL = 3
DQs
DIN A0
DIN A1
DIN A2
DIN A3
Example 2 : Burst Write followed by Precharge: WL = (RL-1) = 4, BL=4 T0 CK/CK T1 T2 T3 T4 T5 T6 T7 T9
CMD
Posted CAS WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Precharge A
Completion of the Burst Write
> = tWR
DQS
WL = 4
DQs
DIN A0
DIN A1
DIN A2
DIN A3
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Auto-Precharge Operation
512M gDDR2 SDRAM
Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Command or the auto-precharge function. When a Read or a Write Command is given to the gDDR2 SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the READ or WRITE Command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write Command is issued, then the autoprecharge function is engaged. During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge on the rising edge which is CAS latency (CL) clock cycles before the end of the read burst. Auto-precharge also be implemented during Write commands. The precharge operation engaged by the Auto precharge command will not begin until the last data of the burst write sequence is properly stored in the memory array. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon CAS latency) thus improving system performance for random data access. The RAS lockout circuit internally delays the Precharge operation until the array restore operation has been completed (tRAS satisfied) so that the auto precharge command may be issued with any read or write command.
Burst Read with Auto Precharge
If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The gDDR2 SDRAM starts an auto Precharge operation on the rising edge which is (AL + BL/2) cycles later than the read with AP command if tRAS(min) and tRTP are satisfied. If tRAS(min) is not satisfied at the edge, the start point of auto-precharge operation will be delayed until tRAS(min) is satisfied. If tRTP(min) is not satisfied at the edge, the start point of auto-precharge operation will be delayed until tRTP(min) is satisfied. In case the internal precharge is pushed out by tRTP, tRP starts at the point where the internal precharge happens (not at the next rising clock edge after this event). So for BL = 4 the minimum time from Read_AP to the next Activate command becomes AL + (tRTP + tRP)* (see example 2) for BL = 8 the time from Read_AP to the next Activate is AL + 2 + (tRTP + tRP)*, where "*" means: "rouded up to the next integer". In any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch. A new bank activate (command) may be issued to the same bank if the following two conditions are satisfied simultaneously. (1) The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins. (2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.
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Example 1: Burst Read Operation with Auto Precharge: RL = 4, AL = 1, CL = 3, BL = 8, tRTP <= 2 clocks
512M gDDR2 SDRAM
T0 CK/CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
Post CAS
READ A Autoprecharge
NOP
NOP
NOP
NOP
NOP
NOP > = tRP
NOP
Bank A Activate
AL + BL/2 clks
DQS
AL = 1 RL =4 CL = 3
DQ's
DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A4 DOUT A5 DOUT A6 DOUT A8
> = tRTP first 4-bit prefetch second 4-bit prefetch tRTP Precharge begins here
Example 2: Burst Read Operation with Auto Precharge: RL = 4, AL = 1, CL = 3, BL = 4, tRTP > 2 clocks T0 CK/CK T1 T2 T3 T4 T5 T6 T7 T8
CMD
Post CAS READ A
Autoprecharge
NOP
NOP
NOP
NOP
NOP
NOP
Bank A Activate
NOP
> = AL + tRTP + tRP
DQS
AL = 1 RL =4 CL = 3
DQ's
DOUT A0 DOUT A1 DOUT A2 DOUT A3
4-bit prefetch
tRTP
Precharge begins here
tRP
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512M gDDR2 SDRAM
Example 3: Burst Read with Auto Precharge Followed by an activation to the Same Bank (tRC Limit): RL = 5 (AL = 2, CL = 3, internal tRCD = 3, BL = 4, tRTP <= 2 clocks)
T0 CK/CK
A10 = 1
T1
T2
T3
T4
T5
T6
T7
T8
CMD
Post CAS READ A
NOP
NOP > = tRas(min)
NOP
NOP
NOP
NOP
NOP
Bank A Activate
Auto Precharge Begins
DQS
AL = 2 RL = 5 CL =3
> = tRP
DOUT A0 DOUT A1 DOUT A2 DOUT A3
DQ's
> = tRC
CL =3
Example 4: Burst Read with Auto Precharge Followed by an Activation to the Same Bank (tRP Limit): RL = 5 (AL = 2, CL = 3, internal tRCD = 3, BL = 4, tRTP <= 2 clocks)
T0 CK/CK
A10 = 1
T1
T2
T3
T4
T5
T6
T7
T8
CMD
Post CAS READ A
NOP
NOP
NOP
NOP
NOP
NOP
Bank A Activate
NOP
> = tRas(min)
Auto Precharge Begins
DQS
AL = 2 RL = 5 CL =3
> = tRP
DOUT A0 DOUT A1 DOUT A2 DOUT A3
DQ's
> = tRC
CL =3
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Burst Write with Auto-Precharge
512M gDDR2 SDRAM
If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The gDDR2 SDRAM automatically begins precharge operation after the completion of the burst write plus write recovery time (tWR). The bank undergoing auto-precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied. (1) The data-in to bank activate delay time (WR + tRP) has been satisfied. (2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.
Burst Write with Auto-Precharge (tRC Limit): WL = 2, tWR =2, tRP=3, BL=4
T0 CK/CK
A10 = 1 Post CAS CMD WRA BankA
T1
T2
T3
T4
T5
T6
T7
Tm
NOP
NOP
NOP
NOP
NOP
NOP Auto Precharge Begins
NOP
Bank A Active
Completion of the Burst Write
DQS/DQS
WL =RL - 1 = 2
> = WR
> = tRP
DQs
DIN A0 DIN A1 DIN A2 DIN A3
> = tRC
Burst Write with Auto-Precharge (tWR + tRP): WL = 4, tWR =2, tRP=3, BL=4 T0 CK/CK
A10 = 1 Post CAS CMD WRA Bank A NOP NOP NOP NOP NOP NOP Auto Precharge Begins NOP Bank A Active
T3
T4
T5
T6
T7
T8
T9
T12
Completion of the Burst Write
DQS/DQS
WL =RL - 1 = 4
> = WR
> = tRP
DQs
DIN A0 DIN A1 DIN A2 DIN A3
> = tRC
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Precharge & Auto Precharge Clarification
From Command Read w/AP Write w/AP Precharge Precharge All To Command Precharge ( to same Bank as Read w/AP) Precharge All Precharge ( to same Bank as Write w/AP) Precharge All Precharge ( to same Bank as Precharge) Precharge All Precharge Precharge All
512M gDDR2 SDRAM
Minimum Delay beween"From Command" to "To Command" AL + BL/2 + tRTP - 2 * tCK AL + BL/2 + tRTP - 2 * tCK WL + BL/2 + WR WL + BL/2 + WR 1 * tCK 1 * tCK 1 * tCK 1 * tCK Unit clks clks clks clks clks clks clks clks Note 1, 2 1, 2 2 2 2 2 2 2
Note : 1. The value of tRTP is decided by the equation : max( RU, 2) where RU stands for round up. This is required to cover the max tCK case, which is 8 ns. 2. For a given bank, the precharge period of tRP should be counted from the latest precharge command issued to that bank. Similarly, the precharge period of tRPall should be counted from the latest precharge all command ossued to the DRAM.
Refresh Command
When CS, RAS and CAS are held low and WE high at the rising edge of the clock, the chip enters the Refresh mode (REF). All banks of the gDDR2 SDRAM must be precharged and idle for a minimum of the Precharge time (tRP) before the Refresh command (REF) can be applied. An address counter, internal to the device, supplies the bank address during the refresh cycle. No control of the external address bus is required once this cycle has started. When the refresh cycle has completed, all banks of the gDDR2 SDRAM will be in the precharged (idle) state. A delay between the Refresh command (REF) and the next Activate command or subsequent Refresh command must be greater than or equal to the Refresh cycle time (tRFC). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight Refresh commands can be posted to any given gDDR2 SDRAM, meaning that the maximum absolute interval between any Refresh command and the next Refresh command is 9 * tREFI. T0 CK/CK
High
T1
T2
T3
Tm
Tn
Tn + 1
CKE CMD
Precharge
> = tRP
> = tRFC
> = tRFC
NOP
NOP
REF
REF
NOP
ANY
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Self Refresh Operation
512M gDDR2 SDRAM
The gDDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. ODT must be turned off before issuing Self Refresh command, by either driving ODT pin low or using EMRS command. Once the Command is registered, CKE must be held low to keep the device in Self Refresh mode. When the gDDR2 SDRAM has entered Self Refresh mode all of the external signals except CKE, are "don't care". Since CKE is an SSTL 2 input, VREF must be maintained during Self Refresh operation. The DRAM initiates a minimum of one one Auto Refresh command internally within tCKE period once it enters Self Refresh mode. The clock is internally disabled during Self Refresh Operation to save power. The minimum time that the gDDR2 SDRAM must remain in Self Refresh mode is tCKE. The user may change the external clock frequency or halt the external clock one clock after Self-Refresh entry is registered, however, the clock must be restarted and stable before the device can exit Self Refresh operation. Once Self Refresh Exit command is registered, a delay equal or longer than the tXSNR or tXSRD must be satisfied before a valid command can be issued to the device. CKE must remain high for the entire Self Refresh exit period tXSRD for proper operation. Upon exit from Self Refresh, the gDDR2 SDRAM can be put back into Self Refresh mode after tXSRD expires. NOP or deselect commands must be registered on each positive clock edge during the Self Refresh exit interval. ODT should also be turned off during tXSRD. Upon exit from Self Refresh, the gDDR2 SDRAM requires a minimum of one extra auto refresh command before it is put back into Self Refresh mode.
T0
T1
T2
T3
T4
T5
T6
Tm
Tn
tCK tCH tCL
CK CK
> = tXSNR tRP* > = tXSRD
CKE
VIL(AC) VIH(AC)
tAOFD
ODT
VIL(AC)
tIS
tIS
tIS tIS tIH
CMD
VIH(AC) VIL(AC)
Self Refresh
VIH(DC) VIL(DC)
NOP
NOP
NOP
Valid
- Device must be in the "All banks idle" state prior to entering Self Refresh mode. - ODT must be turned off tAOFD before entering Self Refresh mode, and can be turned on again when tXSRD timing is satisfied. - tXSRD is applied for a Read or a Read with autoprecharge command. - tXSNR is applied for any command except a Read or a Read with autoprecharge command.
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Power-Down
512M gDDR2 SDRAM
Power-down is synchronously entered when CKE is registered low (along with Nop or Deselect command). CKE is not allowed to go low while mode register or extended mode register command time, or read or write operation is in progress. CKE is allowed to go low while any of other operations such as row activation, precharge or autoprecharge, or auto-refresh is in progress, but power-down IDD spec will not be applied until finishing those operations. Timing diagrams are shown in the following pages with details for entry into power down. The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting power-down mode for proper read operation. DRAM design guarantees it's DLL in a locked state with any CKE intensive operations as long as DRAM controller complies with DRAM specifications. Following figures show two examples of CKE intensive applications. In both examples, DRAM maintains DLL in a locked state throughout the period. CK CK CKE tCKE tCKE tCKE tCKE tCKE
DRAM guarantees all AC and DC timing & voltage specifications and proper DLL operation with intensive CKE operation
CK CK CKE tXP CMD REF tXP REF
tREFI = 7.8 us
The pattern shown above can repeat over a long period of time. With this pattern, DRAM guarantees all DRAM guarantees all AC and DC timing & voltage specifications and DLL operation with temperature and voltage drift.
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512M gDDR2 SDRAM
If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK, ODT and CKE. Also the DLL is disabled upon entering precharge powerdown or slow exit active power-down, but the DLL is kept enabled during fast exit active power-down. In power-down mode, CKE low and a stable clock signal must be maintained at the inputs of the gDDR2 SDRAM, and ODT should be in a valid state but all other input signals are "Don't Care". CKE low must be maintained until tCKE has been satisfied. Power-down duration is limited by 9 times tREFI of the device. The power-down state is synchronously exited when CKE is registered high (along with a Nop or Deselect command). CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied with powerdown exit latency, tXP, tXARD, or tXARDS, after CKE goes high. Power-down exit latency is defined at AC spec table of this data sheet.
Basic Power Down Entry and Exit timing diagram
CK/CK
tIS tIH tIS tIH
VIL(AC)
tIH
VIL(DC)
tIS
VIH(AC)
tIH
VIH(DC)
tIS tIH
VIH(AC) VIH(DC)
CKE Command
VIH(AC) VIH(DC)
VALID tCKE
NOP tCKE
NOP
VALID tXP, tXARD, tXARDS tCKE
VALID
VALID
Enter Power-Down mode Exit Power-Down mode
Don't Care
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Read to power down entry
T0 CK CK CMD CKE DQ DQS DQS T0 T1 T2 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5
AL + CL Q Q Q Q RD BL=4
512M gDDR2 SDRAM
T1
T2
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Tx+7
Tx+8
Tx+9
Read operation starts with a read command and CKE should be kept high until the end of burst operation.
Tx+6
Tx+7
Tx+8
Tx+9
CMD CKE DQ DQS DQS
RD BL=8
CKE should be kept high until the end of burst operation.
AL + CL Q Q Q Q Q Q Q Q
Read with Autoprecharge to power down entry
T0 CK CK CMD
RDA BL=4 PRE AL + BL/2 with tRTP = 7.5ns & tRAS min satisfied AL + CL
T1
T2
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Tx+7
Tx+8
Tx+9
CKE DQ DQS DQS T0 T1 T2
CKE should be kept high until the end of burst operation.
Q Q
Q
Q
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Tx+7
Tx+8
Tx+9
CMD CKE
Start internal precharge
RDA BL=8 AL + BL/2 with tRTP = 7.5ns & tRAS min satisfied AL + CL PRE
CKE should be kept high until the end of burst operation.
DQ DQS DQS
Q
Q
Q
Q
Q
Q
Q
Q
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Write to power down entry
T0 CK CK CMD CKE DQ DQS DQS T0 T1 Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tx
WR BL=4 WL D D D D tWTR
512M gDDR2 SDRAM
Tm Tm+1 Tm+2 Tm+3 Tx Tx+1 Tx+2 Ty Ty+1 Ty+2 Ty+3
T1
Tx+1
Tx+2
Tx+3
Tx+4
CMD CKE DQ DQS DQS
WR BL=8 WL D D D D D D D D tWTR
Write with Autoprecharge to power down entry
T0 CK CK CMD
WRA BL=4 PRE
T1
Tm
Tm+1
Tm+2
Tm+3
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
CKE DQ DQS DQS T0 CK CK CMD CKE DQ DQS DQS
WRA BL=8
WL D D D D WR*1
T1
Tm
Tm+1
Tm+2
Tm+3
Tm+4
Tm+5
Tx
Tx+1
Tx+2
Tx+3
Tx+4
PRE
WL D D D D D D D D WR*1
* 1: WR is programmed through MRS
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Refresh command to power down entry
T0 CK CK CMD CKE
REF
512M gDDR2 SDRAM
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CKE can go to low one clock after an Auto-refresh command
Active command to power down entry
CMD CKE
ACT
CKE can go to low one clock after an Active command
Precharge/Precharge all command to power down entry
CMD CKE
PR or PRA
CKE can go to low one clock after a Precharge or Precharge all command
MRS/EMRS command to power down entry
CMD
MRS or EMRS
CKE
tMRD
Asynchronous CKE Low Event
DRAM requires CKE to be maintained "HIGH" for all valid operations as defined in this data sheet. If CKE asynchronously drops "LOW" during any valid operation DRAM is not guaranteed to preserve the contents of array. If this event occurs, memory controller must satisfy DRAM timing specification tDelay before turning off the clocks. Stable clocks must exist at the input of DRAM before CKE is raised "HIGH" again. DRAM must be fully re-initialized (steps 4 thru 13) as described in initialization sequence. DRAM is ready for normal operation after the initialization sequence. See AC timing parametric table for tDelay specification.
tCK CK# CK CKE tDelay Stable clocks
tIS
CKE asynchronously drops low Clocks can be turned off after this point
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Input Clock Frequency Change during Precharge Power Down
gDDR2 SDRAM input clock frequency can be changed under following condition :
512M gDDR2 SDRAM
gDDR2 SDRAM is in precharged power down mode. ODT must be turned off and CKE must be at logic LOW level. A minimum of 2 clocks must be waited after CKE goes LOW before clock frequency may change. SDRAM input clock frequency is allowed to change only within minimum and maximum operating frequency specified for the particular speed grade. During input clock frequency change, ODT and CKE must be held at stable LOW levels. Once input clock frequency is changed, stable new clocks must be provided to DRAM before precharge power down may be exited and DLL must be RESET via EMRS after precharge power down exit. Depending on new clock frequency an additional MRS command may need to be issued to appropriately set the WR, CL etc.. During DLL re-lock period, ODT must remain off. After the DLL lock time, the DRAM is ready to operate with new clock frequency. Clock Frequency Change in Precharge Power Down Mode T0 CK CK CMD CKE ODT
tRP tAOFD tXP NOP NOP Frequency Change Occurs here NOP NOP DLL RESET NOP Valid
T1
T2
T4
Tx
Tx+1
Ty
Ty+1
Ty+2
Ty+3
Ty+4
Tz
200 Clocks
ODT is off during DLL RESET Minimum 2 clocks required before changing frequency Stable new clock before power down exit
No Operation Command
The No Operation Command should be used in cases when the gDDR2 SDRAM is in an idle or a wait state. The purpose of the No Operation Command (NOP) is to prevent the gDDR2 SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle.
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high at the rising edge of the clock, the RAS, CAS, and WE signals become don't cares.
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Command Truth Table
CKE Function (Extended) Mode Register Set Refresh (REF) Self Refresh Entry Self Refresh Exit Single Bank Precharge Precharge all Banks Bank Activate Write Write with Auto Precharge Read Read with Auto-Precharge No Operation Device Deselect Power Down Entry Power Down Exit Previous Cycle H H H L H H H H H H H H H H L Current Cycle H H L H H H H H H H H X X L H CS L L L H L L L L L L L L L H H L H L RAS L L L X H L L L H H H H H X X H X H CAS L L L X H H H H L L L L H X X H X H WE L H H X H L L H L L H H H X X H X H
512M gDDR2 SDRAM
BA0 BA1 BA X X X BA X BA BA BA BA BA X X X X X X X X X Column Column Column Column X X X X
A11
A10 OP Code X X X L H
A9 - A0
Note 1,2
X X X X X Column Column Column Column X X X X
1 1,8 1,7 1,2 1 1,2 1,2,3 1,2,3 1,2,3 1,2,3 1 1 1,4 1,4
Row Address L H L H X X X X
Note : 1. All gDDR2 SDRAM commands are defined by states of CS, RAS, CAS , WE and CKE at the rising edge of the clock. 2. Bank addresses BA0, BA1, BA2 (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register. 3. Burst reads or writes at BL=4 cannot be terminated or interrupted. See sections "Reads interrupted by a Read" and "Writes interrupted by a Write" 4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements outlined. 5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. 6. "X" means "H or L (but a defined logic level)". 7. Self refresh exit is asynchronous. 8. VREF must be maintained during Self Refresh operation.
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Clock Enable (CKE) Truth Table for Synchronous Transitions
CKE Current State
2
512M gDDR2 SDRAM
Command (N) 3
1
Previous Cycle (N-1) L L L L H H H H
1
Current Cycle (N) L H L H L L L H
Action (N) 3 Maintain Power-Down Power Down Exit Maintain Self Refresh Self Refresh Exit Active Power Down Entry Precharge Power Down Entry Self Refresh Entry
Note 11, 13, 15 4, 8, 11,13 11, 15 4, 5,9 4,8,10,11,13 4, 8, 10,11,13 6, 9, 11,13 7
RAS, CAS, WE, CS X DESELECT or NOP X DESELECT or NOP DESELECT or NOP DESELECT or NOP REFRESH
Power Down Self Refresh Bank(s) Active All Banks Idle
Refer to the Command Truth Table
Note : 1. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge. 2. Current state is the state of the DDR SDRAM immediately prior to clock edge N. 3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N). 4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 5. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied. 6. Self Refresh mode can only be entered from the All Banks Idle state. 7. Must be a legal command as defined in the Command Truth Table. 8. Valid commands for Power Down Entry and Exit are NOP and DESELECT only. 9. Valid commands for Self Refresh Exit are NOP and DESELECT only. 10. Power Down and Self Refresh can not be entered while Read or Write operations, (Extended) Mode Register Set operations or Precharge operations are in progress. See section "Power Down" and "Self Refresh Command" for a detailed list of restrictions. 11. Minimum CKE high time is three clocks.; minimum CKE low time is three clocks. 12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. 13. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the refresh requirements outlined. 14. CKE must be maintained high while the SDRAM is in OCD calibration mode . 15. "X" means "don't care (including floating around VREF)" in Self Refresh and Power Down. However ODT must be driven high or low in Power Down if the ODT function is enabled (Bit A2 or A6 set to "1" in EMRS(1) ). 16. VREF must be maintained during Self Refresh operation.
DM Truth Table Name (Functional) Write enable Write inhibit DM H DQs Valid X Note 1 1
Note : 1. Used to mask write data, provided coincident with the corresponding data
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Input Signal Overshoot/Undershoot Specification
512M gDDR2 SDRAM
AC Overshoot/Undershoot Specification for Address and Control Pins A0-A15, BA0-BA2, CS, RAS, CAS, WE, CKE, ODT Parameter Maximum peak amplitude allowed for overshoot area (See following figyre): Maximum peak amplitude allowed for undershoot area (See following figure): Maximum overshoot area above VDD (See following figure). Maximum undershoot area below VSS (See following figure). Maximum Amplitude Specification - 36 0.9V 0.9V 0.56 V-ns 0.56 V-ns - 2A 0.9V 0.9V 0.45 V-ns 0.45 V-ns
Overshoot Area
Volts (V)
VDD VSS
Maximum Amplitude Time (ns)
Undershoot Area
AC Overshoot and Undershoot Definition for Address and Control Pins
AC Overshoot/Undershoot Specification for Clock, Data, Strobe, and Mask Pins DQ, DQS, DM, CK, CK Parameter Maximum peak amplitude allowed for overshoot area (See following figure): Maximum peak amplitude allowed for undershoot area (See following figure): Maximum overshoot area above VDDQ (See following figure): Maximum undershoot area below VSSQ (See following figure): Maximum Amplitude Specification - 36 0.9V 0.9V 0.28 V-ns 0.28 V-ns -2A 0.9V 0.9V 0.23 V-ns 0.23 V-ns
Overshoot Area
Volts (V)
VDDQ VSSQ
Maximum Amplitude Time (ns)
Undershoot Area
AC Overshoot and Undershoot Definition for Clock, Data, Strobe, and Mask Pins
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Table 1. Full Strength Default Pulldown Driver Characteristics
Pulldown Current (mA) Voltage (V) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Minimum (23.4 Ohms) 8.5 12.1 14.7 16.4 17.8 18.6 19.0 19.3 19.7 19.9 20.0 20.1 20.2 20.3 20.4 20.6 Nominal Default Low (18 ohms) 11.3 16.5 21.2 25.0 28.3 30.9 33.0 34.5 35.5 36.1 36.6 36.9 37.1 37.4 37.6 37.7 37.9
512M gDDR2 SDRAM
Nominal Default High(18 ohms) 11.8 16.8 22.1 27.6 32.4 36.9 40.9 44.6 47.7 50.1 52.2 54.2 55.9 57.1 58.4 59.6 60.9
Maximum (12.6 Ohms) 15.9 23.8 31.8 39.7 47.7 55.0 62.3 69.4 75.3 80.5 84.6 87.7 90.8 92.9 94.9 97.0 99.1 101.1
Figure 1. gDDR2 Default Pulldown Characteristics for Full Strength Driver
120 100 Pulldown current (mA) 80 60 40 20 0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Maximum Nominal Default High Nominal Default Low Minimum
VOUT to VSSQ (V)
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Table 2. Full Strength Default Pullup Driver Characteristics
Pulldown Current (mA) Voltage (V) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Minimum (23.4 Ohms) -8.5 -12.1 -14.7 -16.4 -17.8 -18.6 -19.0 -19.3 -19.7 -19.9 -20.0 -20.1 -20.2 -20.3 -20.4 -20.6 Nominal Default Low (18 ohms) -11.1 -16.0 -20.3 -24.0 -27.2 -29.8 -31.9 -33.4 -34.6 -35.5 -36.2 -36.8 -37.2 -37.7 -38.0 -38.4 -38.6
512M gDDR2 SDRAM
Nominal Default High(18 ohms) -11.8 -17.0 -22.2 -27.5 -32.4 -36.9 -40.8 -44.5 -47.7 -50.4 -52.5 -54.2 -55.9 -57.1 -58.4 -59.6 -60.8
Maximum (12.6 Ohms) -15.9 -23.8 -31.8 -39.7 -47.7 -55.0 -62.3 -69.4 -75.3 -80.5 -84.6 -87.7 -90.8 -92.9 -94.9 -97.0 -99.1 -101.1
Figure 2. gDDR2 Default Pullup Characteristics for Full Strength Output Driver
0 -20 Minimum Pullup current (mA) -40 -60 -80 -100 -120 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Nominal Default Low Nominal Default High Maximum
VDDQ to VOUT (V)
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K4N51163QC-ZC
512M gDDR2 SDRAM
gDDR2 SDRAM Default Output Driver V-I Characteristics gDDR2 SDRAM output driver characteristics are defined for full strength default operation as selected by the EMRS1 bits A7-A9 = `111'. Figures 1 and 2 show the driver characteristics graphically, and tables 1 and 2 show the same data in tabular format suitable for input into simulation tools. The driver characteristics evaluation conditions are: Nominal Default 25 oC (T case), VDDQ = 1.8 V, typical process Minimum TBD oC (T case), VDDQ = 1.7 V, slow-slow process Maximum 0 oC (T case), VDDQ = 1.9 V, fast-fast process Default Output Driver Characteristic Curves Notes: 1) The full variation in driver current from minimum to maximum process, temperature, and voltage will lie within the outer bounding lines of the V-I curve of figures 1 and 2. 2) It is recommended that the "typical" IBIS V-I curve lie within the inner bounding lines of the V-I curves of figures 1 and 2.
Table 3. Full Strength Calibrated Pulldown Driver Characteristics
Calibrated Pulldown Current (mA) Voltage (V) 0.2 0.3 0.4 Nominal Minimum (21 Ohms) 9.5 14.3 18.7 Nominal Low (18.75 ohms) 10.7 16.0 21.0 Nominal (18 ohms) 11.5 16.6 21.6 Nominal High (17.25 ohms) 11.8 17.4 23.0 Nominal Maximum (15 Ohms) 13.3 20.0 27.0
Table 4. Full Strength Calibrated Pullup Driver Characteristics
Calibrated Pulldown Current (mA) Voltage (V) 0.2 0.3 0.4 Nominal Minimum (21 Ohms) -9.5 -14.3 -18.7 Nominal Low (18.75 ohms) -10.7 -16.0 -21.0 Nominal (18 ohms) -11.4 -16.5 -21.2 Nominal High (17.25 ohms) -11.8 -17.4 -23.0 Nominal Maximum (15 Ohms) -13.3 -20.0 -27.0
gDDR2 SDRAM Calibrated Output Driver V-I Characteristics gDDR2 SDRAM output driver characteristics are defined for full strength calibrated operation as selected by the procedure outlined in Off-Chip Driver (OCD) Impedance Adjustment. Tables 3 and 4 show the data in tabular format suitable for input into simulation tools. The nominal points represent a device at exactly 18 ohms. The nominal low and nominal high values represent the range that can be achieved with a maximum 1.5 ohm step size with no calibration error at the exact nominal conditions only (i.e. perfect calibration procedure, 1.5 ohm maximum step size guaranteed by specification). Real system calibration error needs to be added to these values. It must be understood that these V-I curves as represented here or in supplier IBIS models need to be adjusted to a wider range as a result of any system calibration error. Since this is a system specific phenomena, it cannot be quantified here. The values in the calibrated tables represent just the DRAM portion of uncertainty while looking at one DQ only. If the calibration procedure is used, it is possible to cause the device to operate outside the bounds of the default device characteristics tables and figures. In such a situation, the timing parameters in the specification cannot be guaranteed. It is solely up to the system application to ensure that the device is calibrated between the minimum and maximum default values at all times. If this can't be guaranteed by the system calibration procedure, re-calibration policy, and uncertainty with DQ to DQ variation, then it is recommended that only the default values be used. The nominal maximum and minimum values represent the change in impedance from nominal low and high as a result of voltage and temperature change from the nominal condition to the maximum and minimum conditions. If calibrated at an extreme condition, the amount of variation could be as much as from the nominal minimum to the nominal maximum or vice versa. The driver characteristics evaluation conditions are: Nominal 25 oC (T case), VDDQ = 1.8 V, typical process. Nominal Low and Nominal High 25 oC (T case), VDDQ = 1.8 V, any process. Nominal Minimum TBD oC (T case), VDDQ = 1.7 V, any process. Nominal Maximum 0 oC (T case), VDDQ = 1.9 V, any process.
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Rev 1.5 Oct. 2005

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